1. Field of the Invention
The present invention relates to a timing signal generating circuit which performs phase interpolation and a receiver circuit having such a timing signal generating circuit and, more particularly, to a timing signal generating circuit designed to speed up signal transmission between a plurality of LSIs or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or a plurality of cabinets.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of processors and semiconductor memory devices such as DRAMs (Dynamic Random Access Memories). The improvements in the performance of semiconductor memory devices, processors, and the like have come to the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
Specifically, the speed of signal transmission between a main storage device such as a DRAM and a processor (i.e., between LSIs), for example, is becoming a bottleneck impeding performance improvement for a computer as a whole. Furthermore, the need for the improvement of signal transmission speed is increasing not only for signal transmission between cabinets or boards (printed wiring boards), such as between a server and a main storage device or between servers connected via a network, but also for signal transmission between chips or between devices or circuit blocks within a chip because of increasing integration and increasing size of semiconductor chips.
There is therefore a need to provide a timing signal generating circuit that can generate, with simple circuitry and with high accuracy, a plurality of timing signals having a prescribed phase difference synchronously with a reference clock.
To speed up signal transmission between LSIs, it is required that the receiver circuit operates (detects and discriminates data) with accurate timing with respect to an incoming signal. In the prior art, it is known to provide in a signal receiver circuit a clock recovery circuit that uses a feedback loop type clock signal generating circuit (phase adjusting timing signal generating circuit) in order to generate a clock (internal clock) of such accurate timing. Here, the value of a phase adjusting weight for clock recovery is generated using, for example, a phase comparator circuit which compares the phase of an external input clock with that of the internal clock (refer, for example, to Japanese Patent Application No. 2002-25724 (corresponding to U.S. Patent Application Publication No. US2003/0146780 A1) and Japanese Unexamined Patent Publication (Kokai) No. 2002-314516) (corresponding to U.S. Patent Application Publication No. US2002/0172304 A1).
The prior art and its associated problem will be described in detail later with reference to relevant drawings.